rev.9.00 jul. 07, 2004 page 1 of 9 HD151TS305RP spread spectrum clock for emi solution rej03d0021?0900z rev.9.00 jul. 07, 2004 description the hd151ts305 is a high-performance spread spectrum clock modulator. it is suitable for low emi solution. features ? supports 60 mhz to 160 mhz operation. (designed @ sscclkout = 72 mhz) ? 1 copy of finx4 clock out with spread spectrum modulation @3.3 v ? 1 copy of reference clock @3.3 v ? programmable spread spectrum modulation (0.25%, 0.5%, 1.5% central spread modulation and spread spectrum disable mode) ? sop-8pin key specifications ? supply voltages: vdd = 3.3 v 0.165 v ? 0 to 70 c (ta) operating range ? 50 5% outputs clock duty cycle ? cycle to cycle jitter = 250ps typ. ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) HD151TS305RPel sop-8 pin (jedec) fp-8dc rp el (2,500 pcs / reel) note: please consult the sales office for the above package availability. block diagram synthesizer mode control 1/n osc ssc modulator vdd clkout (12mhz typ.) sscclkout (48mhz typ.) gnd sel0 xin xout sel1 1/m r=100 k ? r=100 k ? r=1 m ?
HD151TS305RP rev.9.00 jul. 07, 2004 page 2 of 9 pin arrangement (top view) 8 sel1 1 7 clkout 6 sel0 5 xout sscclkout 2 vdd 3 gnd 4 xin ssc function table sel1 :0 spread percentage 0 0 0.5% 0 1 1.5% 1 0 ssc off 1 1 0.25% note: 0.25% ssc is selected for default by internal pull-up resistors. clock frequency table xin(mhz) sscclkout(mhz) clkout(mhz) 15 60 *1 15 *2 40 160 *1 40 *2 notes: 1. with spread spectrum modulation. 2. without spread spectrum modulation. pin descriptions pin name no. type description gnd 3 ground gnd pin vdd 2 power power supplies pin. normally 3.3 v. clkout 7 output normally 3.3 v reference clock output. sscclkout 1 output spread spectrum modulated clock output. xin 4 input oscillator input. xout 5 output oscillator output. sel0 6 input ssc mode select pin. lvcmos level input. pull-up by internal resistor (100 k ? ). sel1 8 input ssc mode select pin. lvcmos level input. pull?up by internal resistor (100 k ? ).
HD151TS305RP rev.9.00 jul. 07, 2004 page 3 of 9 absolute maximum ratings item symbol ratings unit conditions supply voltage vdd ?0.5 to 4.6 v input voltage v i ?0.5 to 4.6 v output voltage *1 v o ?0.5 to vdd+0.5 v input clamp current i ik ?50 ma v i < 0 output clamp current i ok ?50 ma v o < 0 continuous output current i o 50 ma v o = 0 to vdd maximum power dissipation at ta = 55c (in still air) 0.7 w storage temperature t stg ?65 to +150 c notes: stresses beyond those listed under ?absolute maxi mum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions item symbol min typ max unit conditions supply voltage vdd 3.135 3.3 3.465 v dc input signal voltage ?0.3 ? vdd+0.3 v high level input voltage v ih 2.0 ? vdd+0.3 v low level input voltage v il ?0.3 ? 0.8 v operating temperature t a 0?70c input clock duty cycle 45 50 55 % dc electrical characteristics ta = 0 to 70c, vdd = 3.3 v5% item symbol min typ *1 max unit test conditions input low voltage v il ??0.8v input high voltage v ih 2.0 ? ? v ??10 v i = 0 v or 3.465 v, vdd = 3.465 v, xin pin input current i i ??100 a v i = 0 v or 3.465 v, vdd = 3.465 v, sel0, sel1 pins input slew rate 1 ? 4 v / ns 20% ? 80% input capacitance c i ? ? 4 pf sel0, sel1 operating current ? 20 ? ma xin = 18 mhz, c l = 0 pf, vdd = 3.3 v note: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions.
HD151TS305RP rev.9.00 jul. 07, 2004 page 4 of 9 dc electrical characteristics / cl ock output & ssc clock output ta = 0 to 70c, vdd = 3.3 v5% item symbol min typ max unit test conditions v oh 3.1 ? ? v i oh = ?1 ma, vdd = 3.3 v output voltage v ol ??50mvi ol = 1 ma, vdd = 3.3 v i oh ? ?40 ? v oh = 1.5 v output current * 1 i ol ?40? ma v ol = 1.5 v note: 1. parameters are target of desi gn. not 100% tested in production. ac electrical characteristics / cl ock output & ssc clock output ta = 25c, vdd = 3.3 v, c l = 15 pf item symbol min typ max unit test conditions notes ? | 250 | | 300 | sscclkout = 72mhz, xin = 18 mhz ssc = 0% sel1:0 = 10 fig1 ? | 250 | | 300 | sscclkout = 72mhz, xin = 18 mhz ssc = 0.25% sel1:0 = 11 fig1 cycle to cycle jitter *1, 2 t ccs ? | 250 | | 300 | ps clkout=18mhz fig1 70.4 ? 73.6 sscclkout = 72mhz, xin = 18 mhz ssc = 0% sel1:0 = 10 output frequency *1, 2 70.3 ? 73.7 mhz sscclkout = 72mhz, xin = 18 mhz ssc= 0.25% sel1:0 = 11 slew rate *1 t sl 0.8 ? ? v/ns xin = 18 mhz clkout 0.4 v to 2.4 v clock duty cycle *1 45 50 55 % output impedance *1 ?40? ? spread spectrum modulation frequency *1 ? 33 ? khz sscclkout = 96mhz, xin = 24 mhz input clock frequency 15 ? 40 mhz stabilization time *1,3 ??2 ms note: 1. parameters are target of design. not 100% tested in production. 2. cycle to cycle jitter and output frequency are included spread spectrum modulation. 3. stabilization time is the time required for the integr ated circuit to obtain phase lock of its input signal after power up. sscclkout (or clkout) tcycle n t = (tcycle n) - (tcycle n+1) ccs tcycle n+1 figure 1 cycle to cycle jitter
HD151TS305RP rev.9.00 jul. 07, 2004 page 5 of 9 application information 1. recommended circuit configuration the power supply circuit of the optimal performance on the application of a system should refer to fig. 2. vdd decoupling is important to both reduce jitter and emi radiation. the c1 decoupling capacitor s hould be placed, as close to the vdd pin as possible, otherwise the increased trace inductance will negate its decoupling capability. the c2 decoupling cap acitor shown should be a tantalum type. 8 sel1 1 7 clkout 6 sel0 5 sscclkout 2 vdd 3 gnd gnd gnd 4 xin xout c1 r1 r2 c2 ts300 series (crystal or reference input) (crystal or not connection) notes: c1 = high frequency supply decoupling capacitor. (0.1 f recommended) c2 = low frequency supply decoupling capacitor. (22 f tantalum type recommended) r1, r2 = match value to line impedance. (22 ? reference value) figure 2 recommended circuit configuration
HD151TS305RP rev.9.00 jul. 07, 2004 page 6 of 9 2. example board layout configuration 8 1 7 clkout 6 5 3 4 r2 crystal connection or reference input crystal connection or not connection sscclkout r1 g p g g 0.1 f 22 f fb vdd (+3.3 v supply) g note: via to gnd plane r1, r2 = match value to line impedance. fb = ferrite bead. (22 ? reference value) figure 3 example board layout
HD151TS305RP rev.9.00 jul. 07, 2004 page 7 of 9 3. example of ts300 emi solution ic?s application ts30x t s 3 0 x system bus s y s t e m b u s memory m e m o r y graphics g r a p h i c s system cont. s y s t e m c o n t . ssc s s c clkout c l k o u t spread spectrum s p r e a d s p e c t r u m modulated clock m o d u l a t e d c l o c k cpu & asic c p u & a s i c xtal x t a l ref. r e f . clock c l o c k xin x i n xout x o u t 3.3 v cmos level ref. clock 3 . 3 v c m o s l e v e l r e f . c l o c k fig 4 ref. clock input example ts30x t s 3 0 x system bus s y s t e m b u s memory m e m o r y graphics g r a p h i c s system cont. s y s t e m c o n t . ssc s s c clkout c l k o u t spread spectrum s p r e a d s p e c t r u m modulated clock m o d u l a t e d c l o c k cpu & asic c p u & a s i c xin x i n xout x o u t xtal x t a l fig 5 xtal ref. clock input example
HD151TS305RP rev.9.00 jul. 07, 2004 page 8 of 9 4. recommendation of power?on sequence we recommend usage as power?on sequence vdd starting profile. at the time of power?on starting, there is possibility for sscckout to fix hi/l ow level. please refer fig6?1 and fig6?2. upper 2.8v delay input timing of xin (xin should be applied after vdd 2.8v) xin xout ref. clock vdd xin power on fig 6?1 in case of reference clock input 2.8v (vdd rising time should be applied over 3.5v/msec) xin xout vdd xin minimal rising time power on over 3.5v/msec x' tal fig 6?2 in case of x?tal reference input 5. cycle to cycle jitter we have guaranteed that cycle to cycle jitter will be less than |300ps| at xin=18mhz, vdd=3.3v. in case of using xin will be less than 15mhz, the cycle to cycle jitter may be over |300ps|. please notice to consider this point.
HD151TS305RP rev.9.00 jul. 07, 2004 page 9 of 9 package dimensions package code jedec jeita mass (reference value) fp-8dc conforms ? 0.085 g *dimension including the plating thickness base material dimension 1.75 max 4.90 0.25 0.15 0 ? ? 8 ? m 8 5 1 4 1.27 3.95 0.40 0.06 *0.42 0.08 5.3 max 0.75 max 0.14 + 0.11 ? 0.04 0.20 0.03 *0.22 0.03 0.60 + 0.67 ? 0.20 6.10 + 0.10 ? 0.30 1.08 as of january, 2003 unit: mm
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